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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max2306/max2308/max2309 are if receivers designed for dual-band, dual-mode, and single-mode n-cdma and w-cdma cellular phone systems. the signal path consists of a variable-gain amplifier (vga) and i/q demodulator. the devices feature guaranteed +2.7v operation, a gain control range of over 110db, and high input ip3 (-31dbm at 35db gain, 3.4dbm at -35db gain). unlike similar devices, the max2306 family of receivers includes dual oscillators and synthesizers to form a self-contained if subsystem. the synthesizer? refer- ence and rf dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architec- tures using any common reference and if frequency. the differential baseband outputs have enough band- width to suit both n-cdma and w-cdma systems, and offer saturated output levels of 2.7vp-p at a low +2.75v supply voltage. including the low-noise voltage-con- trolled oscillator (vco) and synthesizer, the max2306 draws only 26ma from a +2.75v supply in cdma (dif- ferential if) mode. the max2306/max2308/max2309 are available in 28- pin thin qfn and qfn packages. applications single/dual/triple-mode cdma handsets globalstar dual-mode handsets wireless data links w-cdma handsets wireless local loop (wll) features ? complete if subsystem includes vco and synthesizer ? supports dual-band, triple-mode operation ? vga with >110db gain control ? quadrature demodulator ? high output level (2.7v) ? programmable charge-pump current ? supports any if frequency between 40mhz and 300mhz ? 3-wire programmable interface ? low supply voltage (+2.7v) max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer ________________________________________________________________ maxim integrated products 1 19-2014; rev 3; 8/04 evaluation kit available pin configurations appear at end of data sheet. block diagram appears at end of data sheet. ordering information selector guide * exposed paddle part temp range pin-package max2306 egi -40 c to +85 c 28 qfn-ep* max2306eti -40 c to +85 c 28 tqfn-ep* max2308 egi -40 c to +85 c 28 qfn-ep* max2308eti -40 c to +85 c 28 tqfn-ep* max2309 egi -40 c to +85 c 28 qfn-ep* max2309eti -40 c to +85 c 28 tqfn-ep* part mode description input range max2306 amps, cellular cdma, pcs cdma dual band, triple mode with two if vcos 40mhz to 300mhz max2308 amps, cellular cdma, pcs cdma dual band, triple mode with common if vco 70mhz to 300mhz max2309 external amps, cellular cdma, pcs cdma dual band, triple mode (drives external amps discriminator) 70mhz to 300mhz
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +2.7v to +3.6v, mode = divsel = shdn = stby = bufen = high, differential output load = 10k ? , t a = -40? to +85?, registers set to default power-up settings. typical values are at v cc = +2.75v and t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +6.0v shdn to gnd.............................................-0.3v to (v cc + 0.3v) stby , bufen , mode, en , data, clk, divsel ...........................................-0.3v to (v cc + 0.3v) vgc to gnd...............-0.3v, the lesser of +4.2v or (v cc + 0.3v) ac signals tankh ? tankl ? ref, fm ? cdma .................................................1.0v peak digital input current shdn , mode, divsel, bufen , data, clk, en , stby .....................................?0ma continuous power dissipation (t a = +70?) 28-pin qfn (derate 28.5mw/? above t a = +70?) ...........2w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units t a = +25? 25.9 37.5 cdma mode t a = -40? to +85? 41.5 t a = +25? 25.4 36.7 fm_iq mode t a = -40? to +85? 40.6 t a = +25? 24.7 35.7 fm_i mode t a = -40? to +85? 39.5 t a = +25? 12.3 18.8 standby (vco_h) t a = -40? to +85? 20.7 t a = +25? 11.4 18.4 standby (vco_l) t a = -40? to +85? 20.3 supply current (note 1) i cc addition for lo out ( bufen = low) 3.5 ma shutdown current i cc shdn = low 1.5 10 ? register shutdown current i cc 4 5.8 ma logic high 2.0 v logic low 0.5 v logic high input current i ih 2a logic low input current i il 2a vgc control input current 0.5v < v vgc < 2.3v -5 5 a vgc control input current during shutdown shdn = low 1 a lock indicator high (locked) 47k ? load 2.0 v lock indicator low (unlocked) 47k ? load 0.5 v dc offset voltage i+ to i- and q+ to q-, pll locked -20 1.5 +20 mv common-mode output voltage v cc = +2.75v v cc - 1.4 v
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 3 ac electrical characteristics (max2306/max2308/max2309 ev kit, v cc = +2.75v, registers set to default power-up states except m1 = m2 = 306, r1 = r2 = 16, f in = 183.7mhz, f ref = 19.2mhz, 0.6vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k ? , all power levels referred to 50 ? , t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units input frequency f in (note 2) 40 300 mhz reference frequency f ref 39 mhz frequency reference signal level v ref 0.2 vp-p signal path, cdma mode gain = -35db, (note 3) 3.4 input 3rd-order intercept iip3 gain = +35db, t a = -40? to +85? (notes 4, 5) -38 -31.0 dbm gain = -35db -9 input 1db compression p 1db gain = +35db -44 dbm gain = -35db -14.8 input 0.25db desensitization (note 6) gain = +35db -49 dbm minimum voltage gain a v v vgc = 0.5v (note 5) -56 -51 db maximum voltage gain a v v vgc = 2.3v (note 5) 57 61 db gain = -35db 62.9 dsb noise figure nf gain = +35db 6.36 dbm signal path, fm_iq mode gain = -35db, (note 7) -6.5 input 3rd-order intercept iip3 gain = +35db, t a = -40? to +85? (notes 5, 8) -40.2 -32 dbm gain = -35db -20 input 1db compression p 1db gain = +35db -44 dbm minimum voltage gain a v v vgc = 0.5v (note 5) -56.7 -52 db maximum voltage gain a v v vgc = 2.3v (note 5) 56 59.5 db signal path, cdma and fm_iq mode gain variation over temperature normalized to +25?c 2.5 db baseband 0.5db bandwidth 4.2 mhz quadrature suppression t a = -40? to +85? (note 5) 28 40 db lo to baseband leakage 1 mvp-p saturated output level v sat differential 2.7 vp-p phase-locked loop f vco _ l (note 2) 80 300 vco tune range f vco _ h (note 2) 135 600 mhz lo_out output power p lo r l = 50 ? , bufen = low -13.7 dbm vco minimum divide ratio m1, m2 256 vco maximum divide ratio m1, m2 16383 ref minimum divide ratio r1, r2 2
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (max2306/max2308/max2309 ev kit, v cc = +2.75v, registers set to default power-up states except m1 = m2 = 306, r1 = r2 = 16, f in = 183.7mhz, f ref = 19.2mhz, 0.6vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k ? , all power levels referred to 50 ? , t a = +25?, unless otherwise noted.) note 1: fm_iq and fm_i modes are not available on max2309. note 2: recommended operating frequency range. contact factory for operating frequency outside this range. note 3: f 1 = 183.7mhz, f 2 = 183.71mhz, p f1 = p f2 = -15dbm. note 4: f 1 = 183.7mhz, f 2 = 183.71mhz, p f1 = p f2 = -50dbm. note 5: guaranteed by design. note 6: small-signal gain at 200khz below the lo frequency will be reduced by less than 0.25db when an interfering signal at 1.25mhz below the lo frequency is applied at the specified level. note 7: f 1 = 183.7mhz, f 2 = 183.71mhz, p f1 = p f2 = -23dbm. note 8: f 1 = 183.7mhz, f 2 = 183.71mhz, p f1 = p f2 = -55dbm. parameter symbol conditions min typ max units ref maximum divide ratio r1, r2 2047 minimum phase detector comparison frequency (note 5) 20 khz maximum phase detector comparison frequency (note 5) 1500 khz 1khz offset, t a = -40? to +85? -79.6 12.5khz offset, t a = -40? to +85? -94.6 30khz offset, t a = -40? to +85? -105 120khz offset, t a = -40? to +85? -115.3 phase noise 900khz offset, t a = -40? to +85? -125 dbc/hz turbo lock acquisition, cpx = xx, tc =1 1480 2100 2650 locked, cpx = 00 105 150 190 locked, cpx = 01 150 210 265 locked, cpx = 10 210 300 380 charge-pump source/sink current locked, cpx = 11 300 425 530 ? charge-pump source/sink matching locked, all values of cpx, 0.5v < v cp < v cc - 0.5v 0.2 10 %
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 5 20.00 25.00 22.50 30.00 27.50 32.50 35.00 2.5 3.5 4.0 3.0 4.5 5.0 5.5 receive supply current vs. supply voltage max2306/8/9 toc01 supply voltage (v) supply current (ma) t a = +85 c t a = +25 c t a = -40 c 0 0.004 0.002 0.008 0.006 0.012 0.010 0.014 2.0 3.0 3.5 2.5 4.0 4.5 5.0 5.5 receive shutdown current vs. supply voltage max2306/8/9 toc02 supply voltage (v) shutdown current (ma) t a = -40 c t a = +25 c t a = +85 c -80 -60 -40 -20 0 20 40 60 80 0.5 1.0 1.5 2.0 2.5 3.0 gain vs. v gc max2306/8/9 toc03 v gc (v) gain (db) t a = +25 c t a = -40 c t a = +85 c 15 25 20 35 30 40 45 55 50 60 0 100 200 300 400 500 gain vs. input frequency max2306/8/9 toc04 frequency (mhz) gain (db) v gc = 2.5v 56.0 57.0 56.5 57.5 59.0 59.5 58.5 58.0 60.0 0 46810 2 1214161820 gain vs. baseband frequency max2306/8/9 toc05 frequency (mhz) relative gain (db) -60 -40 -50 -20 -30 0 -10 10 -60 -20 0 -40 20406080 third-order input intercept vs. gain max2306/8/9 toc06 gain (db) iip3 (dbm) t a = -40 c t a = +85 c t a = +25 c 0 60 20 10 30 40 50 70 -40 -20 -10 0 -30 10 20 50 40 60 30 70 noise figure vs. gain max2306/8/9 toc07 gain (db) nf (db) 6.0 6.4 6.2 6.8 6.6 7.2 7.0 7.4 -40 0 20 -20 406080100 noise figure vs. temperature max2306/8/9 toc08 temperature (?) nf (db) gain = 50db lock vco voltage vco voltage vs. time max2306/8/9 toc09 500 s/div shdn lock time 1.83ms 1v/div typical operating characteristics (max2306/max2308/max2309 ev kits, v cc = +2.75v, registers set to default power-up states, f in = 183.7mhz, f ref = 19.2mhz, synthesizer locked with passive 3rd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k ? , all power levels referred to 50 ? , t a = +25?, unless otherwise noted.)
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 6 _______________________________________________________________________________________ 500 1100 900 700 1300 1500 1700 1900 2100 2300 2500 0 200 100 300 400 500 600 if port parallel resistance vs. frequency max2306/8/9 toc10 frequency (mhz) equivalent parellel resistance ( ? ) measured differentially cdma port fm port max2306/8/9 toc12 -400 -380 -340 -360 -280 -260 -300 -320 -240 equivalent parellel resistance ( ? ) 80 240 320 160 400 480 560 frequency (mhz) tank port parallel resistance vs. frequency tankh tankl measured differentially 0 0.2 0.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 max2306/8/9 toc13 frequency (mhz) equivalent parellel capacitance (pf) 80 160 240 320 400 400 560 tank port parallel capacitance vs. frequency tank tankl measured differentially typical operating characteristics (continued) (max2306/max2308/max2309 ev kits, v cc = +2.75v, registers set to default power-up states, f in = 183.7mhz, f ref = 19.2mhz, synthesizer locked with passive 3rd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k ? , all power levels referred to 50 ? , t a = +25?, unless otherwise noted.) loout port s11 vs. frequency max2310 toc14 start: 10mhz stop: 600mhz 0.5 0.7 0.6 0.9 0.8 1.1 1.0 1.2 0 200 300 100 400 500 600 max2306/8/9 toc11 frequency (mhz) equivalent parellel capacitance (pf) if port parallel capacitance vs. frequency cdma port fm port measured differentially
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 7 pin description pin max2306 max2308 max2309 name function 1, 28 tankl+, tankl- differential tank input for low-frequency oscillator 1, 4 n.c. no connection. must be left open-circuit. 2, 3 2, 3 1, 2 tankh+, tankh- differential tank input for high-frequency oscillator 3 bufen lo buffer amplifier?ctive low 4 mode mode select. high selects cdma mode; low selects fm mode. 4 loout internal vco output. depending on setting of bd bit, loout is either the vco frequency (twice the if frequency) or one-half the vco frequency (equal to the if frequency). 555v cc +2.7v to +5.5v supply 6 6 6 gnd ground 7 7 7 ref reference frequency input 888 shdn shutdown input?ctive low. low powers down entire device, including registers and serial interface. 9, 10 9, 10 9, 10 iout+, iout- differential in-phase baseband output, or fm signal output if fm_i mode is selected. 11 11 11 lock lock output?pen-collector pin. logic high indicates phase-locked condition. 12, 13 12, 13 12, 13 qout-, qout+ differential quadrature-phase baseband output. disabled if fm_i mode is selected. 14 14 14 clk clock input of the 3-wire serial bus 15 15 15 en enable input. when low, input shift register is enabled. 16 16 16 data data input of the 3-wire serial bus. 17 17 17 v cc +2.7v to +5.5v supply 18 18 18 vgc vga gain control input. control voltage range is 0.5v to 2.3v. 19, 20 19, 20 19, 20 cdma-, cdma+ differential cdma input. active in cdma mode. 21 21 fm+ differential positive input. active in fm mode. 22 22 fm- differential negative input for fm signal. bypass to gnd for single-ended operation. 22 stby standby input?ctive low. low powers down vga and demodulator while keeping vco, pll, and serial bus on. 23, 24 23, 24 23, 24 byp bypass node. must be capacitively decoupled (bypassed) to pin 17.
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 8 _______________________________________________________________________________________ _______________detailed description max2306 the max2306 is intended for dual-band (pcs and cel- lular) and dual-mode code division multiple access (cdma) and fm applications (figure 1). the device includes an if variable-gain amplifier, quadrature demodulator, dual vcos, and dual-frequency synthe- sizers (functional diagram ). dual vcos are provided for applications using different if frequencies for each mode or band of operation. the analog fm output sig- nal can be configured for conversion to the i channel, or it may be converted in quadrature to both the i and q channels. the max2306? operation modes are described in table 1. these modes are set by pro- gramming the control register and setting logic levels on control pins. if mode is left floating, the internal reg- ister controls the operation. if driven high or low, mode will override certain register bits, as shown in table 1. max2308 the max2308 supports dual-band, triple mode with common if vco. as with the max2306, the fm mode can be configured for conversion to the i port or quad- rature conversion to both the i and q ports (figure 2). the max2308? operational modes are described in table 2. these modes are set by programming the con- trol register. max2309 the max2309 quadrature demodulators are simplified versions of the max2306 that can be used in single- mode cdma or triple mode using an external fm dis- criminator (figure 3). the max2309 vco is optimized for the 67mhz to 300mhz if frequency range. the max2309 includes a buffered output for the vco. the buffered vco output can be used to support sys- tems implementing traditional limiting if stages for fm demodulation in dual-mode phones as well as for the transmit lo in tdd systems. this buffered output can be configured for the vco frequency (twice the if fre- quency) or one-half the vco frequency (if frequency). the bufen pin enables this feature. a standby mode, in which only the vco and synthesizer are operational, can be selected through the serial interface or the stby pin. the max2309? operational modes are described in table 3. these modes are set by pro- gramming the control register and/or setting logic levels on control pins. if the control pins ( stby , bufen , divsel) are left floating, the internal register controls the operational mode. if driven high or low, the control pins will override certain register bits, as shown in table 3. applications information variable-gain amplifier and demodulator the max2306 family provides a vga with exceptional gain range. the max2306/max2308 support multimode applications with dual differential inputs, selectable with the in_sel (is) control bit. on the max2306, this func- tion can be controlled with the mode pin, which over- rides the is control bit. the vga? gain is controlled over a 110db range with the vgc pin. the output of the vga drives the rf ports of a quadrature demodulator. the max2306/max2308 provide two types of fm demodulation, controlled by the fm_type (ft) control bit. when fm_type is ?,?the signal is passed through both the i and q signal paths for subsequent lowpass filtering and a/d conversion at baseband. if fm_type is ?,?the fm signal is passed through the i mixer only. pin description (continued) pin max2306 max2308 max2309 name function 25 25 25 byp bypass node. must be capacitively decoupled (bypassed) to ground. 26 26 26 cp_out charge-pump output 27 27 27 gnd ground 28 21 n.c. no connection 28 divsel high selects m1/r1; low selects m2/r2. exposed paddle ep ground
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 9 voltage-controlled oscillator, buffers, and quadrature generation the lo signal for downconversion is provided by a voltage-controlled oscillator (vco) consisting of an on- chip differential oscillator, and an off-chip high-q reso- nant network. figure 4 shows a simplified schematic of the vco oscillator. multiband operation is supported by the max2306 with dual vcos. vco_h and vco_l are selectable with the mode pin or the vco_sel (vs) control bit. they oscillate at twice the desired lo fre- quency. for applications requiring an external lo, the vcos can be bypassed with the vco_byp (vb) control bit. the max2309 buffers the output of the vco and pro- vides this signal at the loout pin. this signal is enabled by the bufen (be) control bit or by the bufen control pin. the frequency of this signal is selected by the buf_div (bd) control bit, and can be either the vco frequency or half the vco frequency. quadrature downconversion is realized by providing in- phase (i) and quadrature-phase (q) components of the lo signal to the lo ports of the demodulator described above. the quadrature lo signals are generated by dividing the vco output frequency using two latches. figure 1. max2306 typical operating circuit max2306 byp byp fm- fm+ cdma+ cdma fm 3-wire dac 0.1 f 0.01 f 0.068 f 47pf 2pf 33pf 0.01 f 10k ? 2.4k ? 10k ? 33pf 47pf 33nh 0.01 f 680 ? cdma- lock vgc v cc v cc v cc v cc data clk qout+ qout- en tankh- iout- iout+ ref gnd v cc mode tankh+ tankl- gnd cp_out byp shdn tankl+ 0.01 f v cc 47pf 10k ? 47k ? q 10k ? 2pf 33pf 10k ? 10k ? 33pf i 33nh
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 10 ______________________________________________________________________________________ m s b table 1. max2306 control register states mode shdn pins x l shutdown pin completely powers down the chip shutdown action result operational mode test_mode x cp pol test_en x x turbocharge divsel x vco_byp vco_sel x x x buf_div bufen x x fm_type in_sel x stby shdn ml s control register s bb x x x x x x h x 0 in shutdown register bit leaves serial port active shutdown x x x x x x x 0 x x x 0 x h x 0 in standby register bit turns off vga and modulator only standby x x 1 0 0 h h mode pin overrides vco_sel, divsel, and in_sel to high cdma x x x x x 1 x 1 0 f h floating mode pin returns control to register cdma 1 1 x x 1 1 x 1 0 l h mode pin overrides vco_sel, divsel, and in_sel to low fm_iq x x x x x 1 0 1 0 f h floating mode pin returns control to register fm_iq x x 0 1 0 1 0 l h mode pin overrides vco_sel, divsel, and in_sel to low fm_i x x x x x 1 1 1 0 f h l floating pins return control to register fm_i x x 0 1 1 1 note: h = high, l = low, f = floating pin, x = don? care, blank = independent parameter, 1 = logic high, 0 = logic low. the appropriate latch outputs provide i and q signals at the desired lo frequency. synthesizer the vco? output frequency is controlled by an internal phase-locked-loop (pll) dual-modulus synthesizer. the loop filter is off-chip to simplify loop design for emerg- ing applications. the tunable resonant network is also off-chip for maximum q and for system design flexibili- ty. the vco output frequency is divided down to the desired comparison frequency with the m counter. the m counter consists of a 4-bit a swallow counter and a 10-bit p counter. a reference signal is provided from an external source and is divided down to the comparison frequency with the r counter. the two divided signals are compared with a three-state digital phase-frequen- cy detector. the phase-detector output drives a charge-pump as well as lock-detect logic and tur- bocharge control logic. the charge-pump output (cp_out) pin is processed by the loop filter and drives the tunable resonant network, altering the vco frequen- cy and closing the loop. multimode applications are supported by two indepen- dent programmable registers each for the m counter (m1, m2), the r counter (r1, r2), and the charge-pump output current magnitude (cp1, cp2). the divsel (ds) bit selects which set of registers is used. it can be over- ridden by the max2306? mode pin or the max2309? divsel pin. programming these registers is discussed in the 3-wire interface and registers section.
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 11 m s b table 2. max2308 control register states note: h = high, l = low, 1 = logic high, 0 = logic low, x = don? care, blank = independent parameter stby operational mode 1 1 1 0 x x 0 fm_i fm i operation 0 h 1 0 1 0 x x 0 fm_iq fm iq quadrature operation 0 h 1 x 1 1 x x 0 cdma cdma operation 0 h 0 1 x x 0 standby 0 in standby pin turns off vga and modulator only 0 h x x l x x x x x x shutdown 0 in shutdown register bit leaves seri- al port active x h x x x x x x ml s control register s bb shdn x in_sel fm_type x x bufen buf_div x x x vco_sel vco_byp shutdown shutdown pin completely shuts down chip divsel x l x x turbocharge test_en x cp_pol p i n shdn test_mode action result when the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the turbo feature, enabled by the turbocharge (tc) control bit. turbo functionality provides a larger charge-pump current during acquisition mode. once the vco frequency is acquired, the charge-pump out- put current magnitude automatically returns to the pre- programmed state to maintain loop stability and minimize spurs in the vco output signal. the lock detect output indicates when the pll is locked with a logic high. 3-wire interface and registers the max2306 family incorporates a 3-wire interface for synthesizer programming and device configuration (figure 5). the 3-wire interface consists of clock, data, and enable signals. it controls the vco dividers (m1 and m2), reference frequency dividers (r1 and r2), and a 13-bit control register. the control register is used to set up the operational modes (table 4). the input shift is 17 data bits long and requires a total of 18 clock bits (figure 6). a single clock pulse is required before enable drops low to initialize the data bus. whenever the m or r divide register value is pro- grammed and downloaded, the control register must also be subsequently updated. this prevents turbolock from going active when not desired. the shdn control bit is notable because it differs from the shdn pin. when the shdn control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. in contrast, the shdn pin, when low, shuts down everything, including the registers and seri- al interface. see functional diagram . registers figure 7 shows the programming logic. the 17-bit shift register is programmed by clocking in data at the rising edge of clk. before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the clk input with en high (see figure 6). pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by a0, a1, and a2, respectively (figure 7). table 5 lists the power-on default values of all registers. table 6 lists the charge-pump current, depending on cp0 and cp1.
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 12 ______________________________________________________________________________________ max2308 byp byp fm- fm+ cdma+ 3-wire dac 0.01 f 0.01 f 47pf 2pf 33pf 0.01 f 10k ? 10k ? 33pf 47pf 33nh 0.01 f 680 ? cdma- lock vgc v cc v cc v cc v cc v cc v cc data clk q_out+ q_out- i_out- i_out+ ref gnd v cc tankh- gnd cp_out byp tankh+ 47pf 10k ? 47k ? 10k ? 0.068 f 2.4k ? fm 0.01 f q cdma en shdn figure 2. max2308 typical operating circuit
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 13 table 3. max2309 control register states note: h = high, l = low, 1 = logic high, 0 = logic low, x = don? care, blank = independent parameter. 1 1 1 1 0 1 x 1 x 0 x x shdn stby 1/ 0 x 0 lo buffer enable if pin is floated, then bufen register bit controls buffer h f x x 0 lo buffer enable bufen pin controls the lo buffer and overrides the bit h/ l h x 1/ 0 0 divider select if divsel pin is floated, then register bit selects divider h h f x x 0 divider select divsel pin overrides divsel register bit h h h/ l x 0 standby 0 in standby register bit turns off vga and mod- ulator only h h/ l h x 0 standby 0 in standby pin turns off vga and modulator only l h x x x x x x x x x x shutdown 0 in shutdown register bit leaves serial bus active x h x x x x x x in_sel fm_type x bufen operational mode action result buf_div x x vco_sel vco_byp x x x divsel turbocharge x tes_ten shutdown shutdown pin com- pletely powers down the chip cp_pol x l x x test_mode pins stby x bufen shdn divsel ml s control register s bb
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 14 ______________________________________________________________________________________ max2309 byp byp stby cdma+ 3-wire dac 0.01 f 0.01 f 0.068 f 47pf 2pf 33pf 0.01 f 10k ? 2.4k ? 10k ? 33pf 47pf 33nh 0.01 f 680 ? cdma- lock vgc v cc v cc v cc v cc v cc v cc data clk qout+ qout- en bufen iout- iout+ ref gnd v cc loout tankh- tankh+ gnd cp_out byp shdn divsel 47pf fm 455khz 10k ? 10k ? limiter discriminator 47k ? q i cdma figure 3. max2309 typical operating circuit
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 15 v cc 800 a d1 r1 c f c f r b r l tank_+ tank_- r l r e r e r b figure 4. voltage-controlled oscillators 14-bit m1 counter 14-bit m2 counter 13-bit control register (00) data clk en m u x (010) start bit 16-bit data/address register (011) (11x) (01) vco_h vco_l cpi cp2 f ref cpout 2-bit cp1 11-bit r1 counter 2-bit cp2 11-bit r2 counter figure 5. 3-wire control block diagram
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 16 ______________________________________________________________________________________ msb data clk *sb *start bit must be logic high. lsb en rise and fall required prior to en going low. figure 6. 3-wire interface timing diagram table 4. control register, default state: 0b57 h, address: 110 b sb stby logic ??enables standby mode, which shuts down the vga and demodulator stages, leaving the vco locked and the registers active. 1 ft fm_type active in fm mode. logic ??selects quadrature demodulator for fm mode. logic ??selects downconversion to i port. 1 0 3 sd shdn logic ??enables register-based shutdown. this mode shuts down everything except the m and r latches and the serial bus. 1 0 is in_sel logic ??selects fm input port. logic ??selects cdma input. 1 2 be bufen logic ??disables loout. logic ??enables loout. 1 4 vs vco_sel logic ??selects vco_h. logic ??selects vco_l. 1 ds div_sel logic ??selects m1/r1 divide ratios. logic ??selects m2/r2. 6 1 8 bd buf_div logic ??selects divide-by-2 on loout port. logic ??bypasses divider. 0 5 vb vco_byp logic ??bypasses the vco inputs for external vco operation. 0 7 te test_enable must be 0 for normal operation. 0 10 tc turbo_charge logic ??activates turbocharge mode, which provides rapid fre- quency acquisition in the pll. 1 9 pol cp_pol logic ??causes the charge-pump output cp_out to source cur- rent when f ref /r > f vco /m. this state is used when the vco tune polarity is such that increasing voltage produces increasing fre- quency. logic ??causes cp_out to source current when f vco /m > f ref /r. this state is used when increasing tune voltage causes the vco frequency to decrease. 1 11 bit name function bit id tm test_mode must be 0 for normal operation. 0 12 bit location 0 = lsb power- up state
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 17 cp 2/0 cp 1/1 cp 1/0 r 1/10 cp 2/1 /1 r 2/10 m 1/0 m 1 13 m 2 13 m 2/0 a 2 /m 0 a 1 a 0 a 2 /m 0 a 1 a 0 cp2 and r2 registers shift register m1 register m2 register cp1 and r1 registers ctrl register address decoded start bit 1 00 1 0 0 1 0 1 1 1 0 r 1/0 r 2/0 0 1 tm pol te tc ds vb vs bd be ft is sb sd data figure 7. programming logic default register m2 4269 dec m1 10519 dec ctrl 0b57 hex r2 492 dec r1 492 dec cp1 11 bin cp0 11 bin table 5. register defaults charge-pump current after acquisition (a) cp1 0 210 0 150 cp0 1 0 1 0 1 425 1 300 table 6. charge-pump control bits chip information transistor count: 6422
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer 18 ______________________________________________________________________________________ functional diagram cp1 cp2 m1 register m2 register r1 register r2 register logic sb shift register 1 00 14 11 11 010 011 110 tm pol te tc ds vb vs bd be ft is sb sd data clk control 2 2 2 2 2 ref fm+ fm- cdma+ cdma- iout+ vgc ft vb iout- qout+ qout- lo_out tankl+ vco_l mode ds 14 11 11 14 14 pol 11 2 is vs divsel tankl- tankh+ tankh- lock bd be 2 tc bufen r counter m counter lock det turbo control cp_out charge pump det sb max2309 max2309 sd shdn stby vco_h 14 01 2 bias en max2306 max2308 max2309 max2306 max2309 max2306 max2308
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 19 byp byp fm- fm+ cdma+ dac cdma- lock vga avcc v cc data clk qout+ qout- en tankh- iout- iout+ ref dv cc mode tankh+ tankl- agnd cp_out byp shdn tankl+ /2 0 90 charge pump phase detector /r /m max2306 v cc block diagram
max2306/max2308/max2309 cdma if vgas and i/q demodulators with vco and synthesizer pin configurations 28 27 26 25 24 23 22 tankl- gnd cp_out byp byp byp fm- 8 9 10 11 12 13 14 iout+ iout- lock qout- qout+ clk 15 16 17 18 19 20 21 data v cc vgc cdma- cdma+ fm+ 7 6 5 4 3 2 1 ref gnd v cc mode tankh- tankh+ tankl+ max2306 (t) qfn-ep top view shdn en 28 27 26 25 24 23 22 divsel gnd cp_out byp byp byp 8 9 10 11 12 13 14 iout+ iout- lock qout- qout+ clk 15 16 17 18 19 20 21 data v cc vgc cdma- cdma+ n.c. 7 6 5 4 3 2 1 ref gnd v cc loout tankh- tankh+ max2309 (t) qfn-ep shdn stby en 28 27 26 25 24 23 22 n.c. gnd cp_out byp byp byp fm- 8 9 10 11 12 13 14 iout+ iout- lock qout- qout+ clk 15 16 17 18 19 20 21 data v cc vgc cdma- cdma+ fm+ 7 6 5 4 3 2 1 ref gnd v cc n.c. tankh- tankh+ n.c. max2308 (t) qfn-ep shdn en bufen maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information for the latest package outline information, go to www.maxim-ic.com/packages .
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members max2306 part number table notes: see the max2306 quickview data sheet for further information on this product family or download the max2306 full data sheet (pdf, 208kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max2306egi qfn;28 pin;5x5x0.9mm dwg: 21-0091i (pdf) use pkgcode/variation: g2855-2 * -40c to +85c rohs/lead-free: no materials analysis MAX2306EGI-T qfn;28 pin;5x5x0.9mm dwg: 21-0091i (pdf) use pkgcode/variation: g2855-2 * -40c to +85c rohs/lead-free: no materials analysis max2306eti+t thin qfn;28 pin;5x5x0.8mm dwg: 21-0140k (pdf) use pkgcode/variation: t2855+6 * -40c to +85c rohs/lead-free: yes materials analysis
max2306eti+ thin qfn;28 pin;5x5x0.8mm dwg: 21-0140k (pdf) use pkgcode/variation: t2855+6 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy

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